The present invention relates generally to the field of microprocessor design, and more particularly to design of a microprocessor history buffer.
Some conventional processors use a method called pipelining to improve performance wherein computation is broken up into steps called pipeline stages. For instance, a classical pipeline consists of five stages: fetch, decode, execute, memory, writeback. A branch instruction is an instruction that causes a processor to fetch from a new location, sometimes based on a condition. This condition cannot be fully determined until the branch instruction is executed. To keep the pipeline from stalling while waiting for execution of each branch that is encountered, some processors implement a behavior called branch prediction, where the processor predicts the direction a branch will take, and continues fetching new instructions from the predicted location. If, when the branch is executed, it is determined that the prediction was wrong, instructions younger than the branch that are on the wrongly predicted path must be removed from the pipeline, and fetching must start again from the correct location. This is clearing out of younger instructions is called a pipeline flush (or simply, a flush.) A flush may occur for other reasons as well, for instance: processor state changes that cause subsequent fetches to become invalid; or certain storage-based conditions.
Register renaming is another conventional method used to improve processor performance. A structure called a mapper assigns a physical location (PREG, also sometimes herein referred to as “register tag” or “RTAG”) to a logical register (LREG), to create a LREG to PREG mapping. This allows multiple writers (program instructions) to write to the same LREG while actually writing to different (renamed) PREGs. The processor may then execute (issue) the instructions in an order different from program order, (called out of order execution). The LREG to PREG mapping occurs early in the pipeline process and is performed in program order. Register renaming and corresponding LREG to PREG mapping enables the pipelined instructions to execute concurrently and/or out of order while maintaining integrity of any dependencies that may exist between and among the instructions.